In recent years, consumer electronic devices, such as cellular phones, digital cameras, MP3 players, and personal digital assistant (PDA) devices, have had significant success in the marketplace. The compact design of such consumer electronic devices requires more and more functionalities to be packed into one integrated circuit chip, also referred to as system-on-chip (SoC). In response to this market demand, new semiconductor processing technologies, such as the 90 nm and 65 nm processing technologies, have made it feasible to place millions of logic gates on a single integrated circuit. With such processing technologies, functional blocks such as the central processing unit (CPU), memory, graphic applications, communication modules, and other specialized functions may be integrated onto the SoC.
In addition to more complexity, consumers continue to demand faster time-to-market for such electronic devices, which lead to shorter development cycles for SoCs. To meet this challenge, designers need to evaluate the design goals and cost objectives of a proposed integrated circuit design project long before a full gate-level netlist is available. Early design exploration and floorplanning exercises are aimed at assessing the design goals and cost objectives of an integrated circuit design, often before committing significant engineering resources to the development. These design explorations enable designers to learn about the physical constraints imposed on the design and to guide the front-end design process in the right direction.
FIG. 1 illustrates a conventional approach for exploring an integrated circuit design using black-box design blocks. As shown in FIG. 1, four exemplary functional blocks of a SoC integrated circuit 102 are modeled as black-box design blocks (also known as black-boxes or design blocks for short), shown as 108, 110, 112, and 114. The black-box design blocks are connected to the external pins 104 of the chip through their respective bonding wires 106. Note that a typical SOC integrated circuit may contain many black-box design blocks. Some of these black-box design blocks may be purchased, licensed, or reused (from a prior project). The black-box design blocks are also referred to as intellectual property (IP) blocks, semiconductor IP blocks, virtual design blocks, or virtual circuit components. They include circuit blocks previously designed (typically being reused), circuit blocks currently being developed, or circuit blocks that have not been designed yet.
In this conventional design approach, black-box design blocks are used to represent large functional blocks of the integrated circuit to a level appropriate for top-level design exploration. It allows designers to conduct design exploration and floorplanning exercises before a complete netlist-level description of the design is available. Each of the black-box design blocks generally includes a hard layout extraction format (LEF) physical model, coupled with a timing (.lib) model, which in combination describe the shape and timing of the black-box design block.
Early-on in the design process, many circuit components, such as the CPU, memory interfaces, etc. that will eventually be replaced by gate-level netlists are modeled as black-box design blocks, either because no netlist is currently available, or in order to speed turnaround-time on early floorplan and design-exploration exercises. These circuit components are often referred to as hard-macros or hard physical models because they require fixed shape, pin locations, or routing obstruction information, which hinders the efficiency of early-stage design explorations as will be explained below.
One of the problems of the conventional design exploration using black-box design blocks is that the shapes or pin locations of the black-box design blocks are modified multiple times, often manually, during the design iteration process. This is due to the hard-macro nature of the conventional black-box design block, which has a fixed shape, fixed pin locations along the boundary of the block, and fixed routing obstructions over the block. Designers are required to define the shapes, pin locations, and routing obstructions before they can start the design exploration exercises. During the iterative design exploration exercise, each time the shapes, pin locations, or routing obstructions are modified, the previously defined shapes, pin assignments, or routing obstructions of the black-box design blocks can no longer be used. In other words, since many design exploration iterations require some number of black-boxes to be reshaped and pins to be reassigned, some of the efforts put into the previous iteration of the design are wasted. Designers need to repeat the design of the shapes, pin assignments, or routing obstructions of the black-box design blocks from scratch. This process is inefficient and time consuming.
Therefore, there is a need for conducting design explorations of an integrated circuit.